Many electronic circuits require a pulsed waveform during operational use. Other electronic circuits require a pulsed waveform to fully characterize and test their performance. These electronic circuits typically need a pulse generator which is variable in frequency, pulse height and pulse inversion. The slew rates of the rising and falling edges should be independently adjustable. In addition, pulse generators (driver circuits) for automatic test equipment (ATE) need to be small so that a large number of pulse generators may be located at a test head near a device under test (DUT).
A conventional pulse generator comprising a ramp circuit with variable slew rate control and a buffer is shown in the circuit schematic in FIG. 1. The variable rise and fall slew rates are obtained by alternating the charging and discharging of a capacitor 102 with a first variable current generator 104 and a second variable current generator 106. The charging and discharging operation is accomplished by opening and closing a first switch 108 and a second switch 110. The opening and closing of the switches 108, 110 is synchronized with a clock signal. The voltage on a ramp node 114 represents the voltage across the capacitor. A buffer 112 has an output 124 which replicates the voltage on the ramp node 114 for a variety of load conditions on the output 124.
V-lo 116 is a voltage supply which is connected to a first clamp diode 120 to clamp the ramp node 114 from going more than one diode voltage drop below V-lo 116. Similarly, V-hi 118 is a voltage supply which is connected to a second clamp diode 122 to clamp the ramp node 114 from going higher than one diode voltage drop above V-hi 118. By controlling both V-lo 116 and V-hi 118, the ramp node 114 voltage and consequently the output 124 of the buffer 112 can be contained within a predetermined range of voltages.
The value chosen for the capacitor 102, the current IB of the first current generator 104 and the current IA of the second current generator 106 control the rise and fall times of the pulsed output signal. In this circuit configuration, the second current generator 106 controls the rise slew rate and the first current generator 104 controls the fall slew rate. The second current generator 106 is a source of current because current from the generator 106 flows into the capacitor 102 and the first current source 104 is a sink of current because current from the generator 104 flows out of the capacitor 102.
The sequence of operation may be described as follows. When the clock signal is in a first state, the first switch 108 is closed and the second switch 110 is opened. The capacitor 102 will discharge to the point that the ramp node 114 is one diode voltage drop below V-lo 116. When the clock signal transitions to a second state, the second switch 110 is closed and the first switch 108 is opened simultaneously. Sink current of the first current source 104 is interrupted and the source current of the second current source 106 is applied to the ramp node 114. The ramp capacitor 102 will charge up until the voltage on the ramp node 114 is clamped by the second diode 122 turning on. This will occur when the voltage at the ramp node 114 is one diode voltage drop above V-hi 118. The rising slew rate of the ramp node 114 is proportional to the source current IA of the second current source 106 applied and inversely proportional to the capacitance on the ramp node 114. Similarly, when the settings of the switches are reversed, the falling slew rate is proportional to the sink current IB of the first current source 104 applied and inversely proportional to the capacitance on the ramp node 114.
It is desirable to have the slew rates be constant during the rising and falling of a voltage pulse. This requires that the source and sink currents provide a constant current flow into or out of the ramp node 114. The source and sink currents may be of different magnitudes so that the rise slew rate and fall slew rate are different. This allows for a fast rise time and a slow fall time pulse or a slow rise time and a fast fall time pulse.
When the voltage at the ramp node 114 has ramped up to or down to its final voltage, the capacitor 102 is no longer being charged. The current IA or IB will flow through either the first diode 120 or the second diode 122 exclusively. The current IA of the second current source 106 and the current IB of the first current source 104 are variable. The voltage across a diode is slightly dependent on the current flowing through it. Therefore, the voltage across the first diode 120 or the second diode 122 is also variable. As a result, the accuracy of the voltage at the ramp node 114 can be poor. In addition, the diodes are temperature sensitive which can cream errors over any temperature operating range.
Most pulse generators require linear slew rates which requires constant charging currents for the first current source 104 and the second current source 106. For the second current source 106, current is being sourced to a ramp node 114 rather than taken from the ramp node 114. When implemented on an integrated circuit, this generally implies the use of PNP transistors and the switching of such transistors is slow. In addition, the second switch 110 and possibly the second current source 106 add extra capacitance to the ramp node 114. This extra capacitance slows the speed of operation considerably and limits the maximum slew rate possible.
FIG. 2A shows the control signal to the second switch 110. FIG. 2B shows the control signal to the first switch 108. FIG. 2C shows the output signal of the buffer 112. The time T1 at which the second switch is closed and the first switch is opened defines the beginning of rising edge 125 of the output signal 2C. The time T2 at which the second switch is opened and the first switch is closed defines the beginning of the falling edge of the output signal 2C.
For electronic circuit operation and test, there is a need for a pulse generator with adjustment capabilities of the slew rates of the rising and falling edges and variability in the waveform frequency, pulse height, pulse inversion. The pulse waveform parameters should be accurate and not vary with temperature. In addition, it is desirable that the pulse generator be physically small so that a large number of pulse generators may be located at a test head near a device under test (DUT).